In the integrated circuit (IC) industry, the performance of metal oxide semiconductor (MOS) field effect transistor (FETs) are controlled by two primary device characteristics. The performance of a MOSFET device can be enhanced by reducing the length of a gate electrode of the MOSFET device, and/or reducing the gate dielectric thickness of the MOSFET device. The integrated circuit industry has progressed to a point where thermal gate oxide thickness is becoming less than roughly 60 angstroms. As gate dielectrics progress to a thickness less than 60 angstroms, a theoretical and practical limit to thermal gate oxidation is now being approached. Therefore, the integrated circuit industry is attempting to develop materials which can replace thermal oxides as gate dielectric materials in order to continue to progress the performance of MOS transistors to new levels.
For this purpose, high-k metal oxide materials have been proposed as a potential gate dielectric to replace thermal oxide gate dielectrics. Since the dielectric constant of metal oxide material is made greater than that of thermal oxide, a thicker metal oxide can be physically deposited while achieving a similar equivalent oxide thickness (EOT) of a thinner thermal oxide gate dielectric. For the purpose of illustration, a metal oxide gate dielectric deposited to a thickness of roughly 80 angstroms could be roughly equivalent to a thermal oxide gate dielectric deposited to a thickness of 20 angstroms in terms of MOSFET performance whereby thinner EOTs are more advantageous to MOSFET performance. This physical increase in gate dielectric thickness while maintaining similar levels of EOT/performance is advantageous since the physically thicker metal oxide can reduce gate-to-channel leakage current while MOSFET performance is not adversely impacted.
A first prior art solution for forming high-k metal gates in semiconductor devices has used tantalum pentoxide as a barrier formed over the semiconductor substrate. Following the formation of the tantalum pentoxide layer an anneal step has been performed. However, the step of annealing caused the formation of a silicon dioxide layer at the tantalum pentoxide and silicon substrate interface. This silicon dioxide barrier has been shown to be approximately 20-40 angstroms thick. Following the anneal step, a metal gate was formed over a top of the tantalum pentoxide. The overall effect of the metal tantalum pentoxide/silicon dioxide gate dielectric structure is the formation of series connected capacitors to be formed from the surface of the gate to the substrate. One of the capacitors is formed by the metal gate dielectric that has a higher dielectric constant while the second such capacitor is formed by the silicon dioxide layer that has a much lower dielectric constant. The results of this structure is such that the capacitance of the small-k dielectric material dominates whereby the improvement of the higher k metal oxide is reduced.
A second prior art method of using metal gates over silicon substrates formed a chemically grown SiO.sub.2 layer over the silicon substrate. The advantage of growing the SiO.sub.2 layer is that its thickness can be precisely controlled to approximately 20 angstroms and the SiO.sub.2 interface state density of the Si interface is low. Subsequently, a tantalum pentoxide layer is formed on top of the silicon dioxide layer and a metal gate subsequently formed over of the tantalum pentoxide. While this prior art method reduces the thickness of the silicon dioxide over the previously discussed prior art method, the problem remains the same in that a capacitance formed by the silicon dioxide layer is such that it dominates the high-k dielectric layer whereby the improvement in the gate dielectric EOT is self-limited.
Therefore, it would be advantageous to form a metal gate structure whereby the dominant capacitance effects of a silicon dioxide layer are minimized.